Metal-oxide-semiconductor (MOS) devices are basic building elements in integrated circuits. In conventional MOS devices, gate electrodes often comprise polysilicon doped with p-type or n-type impurities, using doping operations such as ion implantation or thermal diffusion. FIG. 1 illustrates a conventional MOS device having an implanted gate electrode. In a typical formation process, after forming a gate stack including gate dielectric 4 and polysilicon gate electrode 6, implantations are performed to dope impurities. The implantations typically include an implantation to form lightly-doped source and drain regions and an implantation to form deep source and drain regions.
MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, also referred to as a poly depletion effect (also known as polysilicon depletion). The poly depletion effect occurs when an applied electric field sweeps away carriers from a region of gate electrode 6 close to gate dielectric 4, forming a depletion layer. In n-doped polysilicon, the depletion layer includes ionized non-mobile donor sites. Whereas in p-doped polysilicon, the depletion layer includes ionized non-mobile acceptor sites. The depletion effect increases the effective gate dielectric thickness, making it more difficult for an inversion layer to be created at the surface of the semiconductor.
Typically, implanted impurities have a high doping concentration in an upper portion of gate electrode 6, while in region 8 of gate electrode 6, which is a lower portion close to gate dielectric 4, the impurity concentration is low. The low impurity concentration at the interface region of gate electrode 6 and gate dielectric 4 increases the likelihood of poly depletion.
FIG. 2 illustrates an intermediate stage of a method for solving the poly depletion problem. After a gate dielectric layer 12 is formed on substrate 10, polysilicon layer 14 is formed on gate dielectric layer 12. Polysilicon layer 14 is in-situ doped during its formation with a p-type or an n-type impurity. Assuming a p-type impurity is in-situ doped, a portion of polysilicon layer 14 in NMOS region 16 is removed, exposing underlying gate dielectric layer 12, while a portion of polysilicon layer 14 in PMOS region 18 is left un-removed. In subsequent steps, as shown in FIG. 3, polysilicon layer 20, which is in-situ doped with an n-type impurity, is formed in NMOS region 16. In subsequent steps, polysilicon layers 14 and 20 are then patterned to formed gate stacks. By in-situ doping impurities, the interface regions will have high impurity concentrations, and the polysilicon depletion problem is solved.
The removal of polysilicon layer 14 from NMOS region 16, however, will cause a top portion of the underlying gate dielectric layer 12 to be removed, thus resulting in variations in the thickness of the gate dielectric layer 12. Variations in the thickness of gate dielectrics in the resulting MOS devices undesirably affect the performance of the MOS devices. In advanced technologies, wherein the thickness of gate dielectric layer 12 is reduced to about 15 Å or below, the variations in the thickness of gate dielectrics is significant. A solution is thus needed to eliminate, or at least reduce, the thickness variations.